In current wafer level chip scale package (WLSCP), four masks that include one under ball metal (UBM) layer, one redistribution layer (RDL), and two polymer layers are implemented in the processing of the current 8″ and 12″ integrated circuit wafers for wafer level chip scale packaging. There are now four processes that include coating, photolithography exposure, and developing required in WLCSP process. This makes package cost relatively high.
WLCSP processing may include two masks for forming a UBM layer and a polymer layer with direct ball drop. The two mask process of the WLCSP has many drawbacks that include layer cracking in a 55 nm low k dielectric layer during surface mount technology (SMT) processing and requiring extra underfill material to pass board level reliability (BLR) during thermal cycling of the printed circuit board test. These drawbacks limit of the package size.
“A Reliable Wafer-level Chip Scale Package (WLSCP) Technology}, Sharma, Holland et al., International Wafer Level Packaging Conference 2007 Proceedings, September, 2007, describes a conventional two mask process WLCSP process, after defining the under bump metal (UBM) layer, a solder ball is dropped in the UBM opening. A subsequent thermal reflow cycle melts the solder ball and cools it in a well defined shape on top of the UBM layer. Sharma et al. systematically analyzes the problem of passivation cracking and presents a WLCSP process that is resistant to cracking during solder flow and subsequent multiple reflow steps.
“Technology Solutions for a Dynamic and Diverse WLCSP Market”, Chilukuri, Chip Scale Review, March/April 2011, Volume 15, Number 2, pp.: 16-19, describes two mask and four mask WLCSP processes and examines material options i.e., polymers and solder alloys for these new structures and the effects of die sizes and I/O counts on product reliability. Board level reliability (BLR) data and analyses of the failure modes is presented.
FIG. 1 is a cross-sectional diagram of a four-mask process for forming a ball bond connection system of an integrated circuit chip for connecting to a second level packaging (board or module) for wafer level chip scale packages as described in Chilukuri of the prior art. Referring now FIG. 1, the wafer 5 has been processed to embed electronic circuitry into the surface of the wafer 5 for each integrated circuit chip. After the embedding of the electronic circuitry, the surface of the wafer 5 is coated with a passivation layer 15 to protect the electronic circuitry. The surface of the passivation layer 15 has openings that align with the input/output contacts 10 of the embedded electronic circuitry. A first mask is placed over the wafer covering the locations of the opening aligned with the input/output contacts 10. The wafer 5 is coated with a first insulating material 20 over the passivation layer 15. A second mask is placed on the first insulating material 20. Openings in the second mask provide access of the redistribution layer (RDL) 30 to the input/output contacts 10. A third mask is applied to the surface of the wafer 5. Openings in the third mask define the paths of the redistribution layer (RDL) 30. The redistribution layer (RDL) 30 is a metal layer formed over the surface of the first insulating material 20 to make the input/output contacts 10 of the integrated circuit available in other locations, such as the location of an input/output connector 40 for connection to the second level package. A second insulating material 25 is placed on the surface of the wafer 5. A fourth mask is placed over the surface of the wafer 5 with openings at a location where the input/output connector 40 is to be placed. The under ball metal (UBM) 35 is formed within the opening of the second insulating material 25. In this example, the input/output connector 40 is a solder ball that is placed with the opening of the second insulating layer 25. The solder ball 40 solder balls are reflowed onto the under ball metal 35 creating a large standoff.
FIG. 2 is a cross-sectional diagram of a two-mask process for attaching and connecting chip to second level packaging (board or module) for wafer level chip scale packages as described in Sharma et al. and Chilukuri. Referring now to FIG. 2, the wafer 105 has been processed to embed electronic circuitry into the surface of the wafer 105 for each integrated circuit chip. After the embedding of the electronic circuitry, the surface of the wafer 105 is coated with a passivation layer 115 to protect the electronic circuitry. The surface of the passivation layer 115 has openings that align with the input/output contacts 110 of the embedded electronic circuitry. The openings are filled with a metal such as aluminum or copper to contact the input/output contact 110. A first mask is placed on the passivation layer 115 with openings that define the paths of the redistribution layer (RDL) 130. The redistribution layer (RDL) 130 is a metal layer formed over the surface of the passivation layer 115 to make the input/output contacts 110 of the integrated circuit available in other locations, such as the location of an input/output connector 140 for connection to the second level package. A second insulating material 125 is placed on the surface of the surface of the wafer 105. A second mask is placed over the surface of the wafer 105 with openings at a location where the input/output connector 140 is to be placed. The under ball metal (UBM) 135 is formed within the opening of the second insulating material 125. In this example, the input/output connector 140 is a solder ball that is placed with the opening of the second insulating layer 125. The solder balls 140 are reflowed onto the under ball metal 135 creating a large standoff.